This invention relates to data processors such as calculators, micro-controllers, microprocessors, digital signal processors, central processing units of microcomputers, minicomputers, and large-scale computers generally. This invention relates to U.S. Pat. No. 4,680,701, issued Jul. 14, 1987 to Michael J. Cochran, and U.S. Pat. No. 3,290,511, issued Dec. 6, 1966 to John C. Sims.
Modern data processors are usually built as digital electrical circuits and the several logic elements thereof are designed to operate on a fixed time scale determined by a clock source forming an inherent part of the circuit. For instance, let L1 and L2 be two components of the circuit. L1 can be the component that decodes instructions in a processor, and L2 can be the arithmetic and logical unit (ALU) of the processor. L1 gets an instruction x and produces a decoded instruction y. After that, L2 takes y and produces the result z of the instruction. For L2 to start computing z only after the result y of L1 is valid, a sequencing means must be part of the circuit. Such a means is usually a clock, the operation of which relies on the knowledge of the durations of the operations of L1 and L2. More precisely, if a clock signal triggers L1 at time t to start the computation of y, and if the computation requires less than d units of time in all cases, then another clock signal may trigger L2 at time t+d to start the computation of z. All present data processors we know of use a clock scheme and are therefore said to be "synchronous".
Observe that in order to function correctly, the clock scheme between components L1 and L2 in the example above must use the worst-case delay for d, including some provision for the skewing of the clock signals as they are distributed across the circuit. This serious drawback of synchronous techniques has been known for as long as such techniques have been used and is well explained in U.S. Pat. No. 3,290,511.
The difficulties and inefficiencies inherent to synchronous techniques have been exacerbated by the advent of Very-Large-Scale-Integration (VLSI) semiconductor technology, in which possibly very large electrical circuits can be integrated on one piece of semiconductor material, for instance silicon. (Such an integrated circuit is usually called a "chip".) Improvement in performance of VLSI circuits is achieved mainly through decrease in the physical dimensions of the basic features of the circuit. But continued miniaturization of integrated circuits has adversary side-effects with respect to the use of clocks.
First, the decrease in size of all physical parameters of a circuit (usually called "scaling" in the literature) has for a result that the transmission delays in the wires connecting logical elements increase relatively to the switching delays of the elements themselves. (This phenomenon is well explained in the literature. See, for instance, Reference 9.) As a consequence, the transmission of a clock signal from one point of a circuit to several other ones becomes more and more difficult if the signals are to arrive at about the same time at the different points. This phenomenon is called "clock skew" and is a major problem in the design of clocked electronic circuits. In particular, the designer may have to increase the clock period to accommodate the clock skew. Another consequence of increased wire delays is that the layout of the circuits (i.e. the physical placement of the elements on the surface and the wiring of the elements) has to be done very carefully since the proper functioning of the circuit may critically depend on the lengths of the wires.
A second adversary side-effect of miniaturization is that controlling the physical parameters of the fabrication process becomes more and more difficult. Less control on the fabrication process results in an increased variation in the physical parameters of the chip, such as noise margin, switching thresholds, resistance and capacitance of nodes, etc. An accurate evaluation of these parameters is essential to a precise estimate of the worst-case duration of a computation step. Therefore, a lack of accuracy in the evaluation of these parameters results in increased clock period and less tolerance to the variations of the operating parameters, in particular, voltage level and temperature.
Because a precise adjustment of the clock period implies a comparison and calibration of all elements of a chip, modification of a circuit usually requires a complete redesign of the whole circuit. Hence, it is notoriously difficult for a manufacturer to develop a line of products in which each is an incremental improvement of the preceding one.